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Title:
SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF
Document Type and Number:
Japanese Patent JP2008098624
Kind Code:
A
Abstract:

To provide a transistor structure capable of improving an ESD resistance.

In the semiconductor apparatus, a drain layer 12 with high concentration is formed apart from an edge of drain side of a gate electrode 7 on a surface of a drain layer 10 with intermediate concentration. A P-type impurity layer 13 is formed on a surface of a substrate between the gate electrode 7 and the drain layer 12 with high concentration so as to surround the drain layer 12 with high concentration. During a parasitic bipolar transistor 30 turns on due to abnormal surge voltage, electrons move from a source electrode 15 side to a drain electrode 16 side. In this case, electrons avoid the vicinity of the surface of the substrate X on which the P-type impurity layer 13 is formed, as shown by the arrow 25 in Fig. 4, electrons are dispersed and moved so as to infiltrate into a side of drain electrode 16 from deeper location.


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Inventors:
YATSUYANAGI TOSHISUKE
UEHARA MASABUMI
ANZAI KATSUYOSHI
Application Number:
JP2007235676A
Publication Date:
April 24, 2008
Filing Date:
September 11, 2007
Export Citation:
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Assignee:
SANYO ELECTRIC CO
SANYO SEMICONDUCTOR CO LTD
International Classes:
H01L29/78
Domestic Patent References:
JPH08172184A1996-07-02
JP2000183181A2000-06-30
JP2003218348A2003-07-31
JP2001320047A2001-11-16
JP2006114768A2006-04-27
JPS63314869A1988-12-22
JP2002043579A2002-02-08
JP2005109483A2005-04-21
JPH08172184A1996-07-02
JP2000183181A2000-06-30
JP2003218348A2003-07-31
Foreign References:
US6144070A2000-11-07
Attorney, Agent or Firm:
Hiroshi Kakutani



 
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