Title:
SEMICONDUCTOR APPARATUS
Document Type and Number:
Japanese Patent JP2006140271
Kind Code:
A
Abstract:
To provide a semiconductor apparatus improved in reliability of an MEMS device.
The semiconductor apparatus comprises a surface MEMS device, a semiconductor substrate 11, and actuators 22a and 22b. The actuators 22a, 22b are arranged above the semiconductor substrate 11 with a space 34; and comprises a lower electrode 19, upper electrode 21, and a piezoelectric layer 20 sandwiched between the lower electrode 19 and the upper electrode 21. At least the entire surface of the piezoelectric layer 20 among the lower electrode 19, upper electrode 21, and piezoelectric layer 20 is almost flat.
Inventors:
OGURO TATSUYA
SEKINE SHUICHI
IKEHASHI TAMIO
MATSUO MIE
SEKINE SHUICHI
IKEHASHI TAMIO
MATSUO MIE
Application Number:
JP2004327727A
Publication Date:
June 01, 2006
Filing Date:
November 11, 2004
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
H01L41/08; H01H57/00; H01L21/329; H01L21/822; H01L21/8234; H01L21/8246; H01L27/04; H01L27/06; H01L27/105; H01L29/93; H01L41/09; H01L41/18; H01L41/187; H01L41/193; H01L41/22; H01L41/311; H04R17/00
Domestic Patent References:
| JP2000031397A | 2000-01-28 | |||
| JPH06120416A | 1994-04-28 | |||
| JPH0629741A | 1994-02-04 | |||
| JPS63120481A | 1988-05-24 | |||
| JPS60211986A | 1985-10-24 | |||
| JP2004127973A | 2004-04-22 |
Attorney, Agent or Firm:
Takehiko Suzue
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto
Previous Patent: MOUNTING METHOD OF ELECTRONIC DEVICE, CIRCUIT BOARD, AND ELECTRONIC EQUIPMENT
Next Patent: ELECTROMAGNETIC CONTROL VALVE
Next Patent: ELECTROMAGNETIC CONTROL VALVE