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Patent Searching and Data

Document Type and Number:
Japanese Patent JPS5612762
Kind Code:

PURPOSE: To elevate the capacity and the withstanding voltage of a semiconductor capacity element by a method wherein a uniconductive first region is formed on the surface of a semiconductor, another conductive second region is formed coming in contact with the center part of base face of the first region and a third region to take out an electrode from the second region is formed.

CONSTITUTION: An N-type high density impurity region 12 is formed on a P-type silicon substrate 11, and a P-type high density impurity region 20 is formed on it by diffusion. An N-type epitaxial layer 13 is made to grow on it, and a P-type impurity is made to diffuse from two appointed points of the surface of the epitaxial layer 13 reaching to the region 20 to form simultaneously P-type high density impurity regions 21 and 22. An N-type impurity is made to diffuse to form an N-type region 15 having higher density than the region 21 to cover the region 21 making the side face to come out completely from the region 21 but not to come in contact with the region 22. Openings are made in an oxide film 16 on the surface of the epitaxial layer 13, and electrodes C, D are installed through the openings.

Wakabayashi, Hiroyuki
Application Number:
Publication Date:
February 07, 1981
Filing Date:
July 10, 1979
Export Citation:
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International Classes:
H01L21/822; H01L27/04; H01L29/93; (IPC1-7): H01L29/93