Title:
SEMICONDUCTOR CHIP PACKAGE AND ITS MANUFACTURE
Document Type and Number:
Japanese Patent JPH02297947
Kind Code:
A
Abstract:
PURPOSE: To improve productive efficiency and repairing efficiency by using single step bonding wires of uniform length for bonding a semiconductor chip package. CONSTITUTION: A semiconductor chip package 20 contains a top surface 22 having a recessed chip holding void 26, and the top surface 22 has a junction pad 14 assigned in a single step pattern. The void 26 contains a semiconductor chip 30 having a chip junction pad 32. Bonding wires 36 of uniform length connect the package junction pads 14 and the chip junction pads 32. As a result, electrical disturbances or crosstalks between the adjacent wires is minimized, and productivity efficiency and repairing efficiency are enhanced.
Inventors:
TOOMASU JIEI DANAUEI
RICHIYAADO KEI SUPIIRUBAAGAA
RICHIYAADO KEI SUPIIRUBAAGAA
Application Number:
JP3229490A
Publication Date:
December 10, 1990
Filing Date:
February 13, 1990
Export Citation:
Assignee:
HONEYWELL INC
International Classes:
H01L21/60; H01L23/498; (IPC1-7): H01L21/60
Attorney, Agent or Firm:
Masaki Yamakawa (4 outside)
Previous Patent: MANUFACTURE OF SEMICONDUCTOR ELEMENT PACKAGE
Next Patent: WIRE BONDING AND DEVICE THEREFOR
Next Patent: WIRE BONDING AND DEVICE THEREFOR