Title:
SEMICONDUCTOR CIRCUIT
Document Type and Number:
Japanese Patent JP2019047208
Kind Code:
A
Abstract:
To improve reliability by performing resynchronization quickly, even if synchronization is lost for some reason.SOLUTION: A semiconductor circuit includes multiple transmission circuits to which synchronized first clocks are inputted, respectively. Each of the multiple transmission circuits includes a divider circuit outputting a third clock signal, generated by dividing a frequency of an unsynchronized second clock signal and synchronized with the first clock signal, a phase comparator for comparing phases of the first and third clock signals, and a reset signal generator for setting the first signal to a first logical level for a prescribed period, when phase shift is detected by the phase comparator. When the phase shift is detected by the phase comparator, the divider circuit is reset while the first signal has the first logical level, and when the first signal changes subsequently from the first logical level to the second logical level, a reset state is cancelled, and the third clock signal synchronized with the first clock signal is generated again.SELECTED DRAWING: Figure 1
Inventors:
NAGAMITSU MASATOMO
Application Number:
JP2017165864A
Publication Date:
March 22, 2019
Filing Date:
August 30, 2017
Export Citation:
Assignee:
TOSHIBA MEMORY CORP
International Classes:
H04L7/00; G06F1/04; G06F1/12; H03K21/40
Attorney, Agent or Firm:
Hiroyuki Nagai
Yukitaka Nakamura
Yasukazu Sato
Satoru Asakura
Takeshi Sekine
Akaoka Akira
Yasushi Kawasaki
Yukitaka Nakamura
Yasukazu Sato
Satoru Asakura
Takeshi Sekine
Akaoka Akira
Yasushi Kawasaki