Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
SEMICONDUCTOR CIRCUIT
Document Type and Number:
Japanese Patent JP3696004
Kind Code:
B2
Abstract:

PROBLEM TO BE SOLVED: To provide a semiconductor circuit wherein respective outputs of cascaded flip-flops never reach unintended values.
SOLUTION: This semiconductor circuit is constituted by cascading (n) register circuits REG0 to REGn-1. Each register circuit select a signal inputted to its 1st or 2nd input terminal IN1 or IN2 based on the logic of a shift direction selection/switching signal X. Each of the register circuits other than the initial stage inputs the output of its precedent register circuit at the rise of a clock CK when the signal X is '1', and inputs the output of the succeeding register circuit at the rise of the clock signal CK when the signal X is '0'. The initial- stage register circuit inputs the output of the register circuit of the final stage when the signal X is '1', and inputs the output of the register circuit of the 2nd stage when the signal X is '0'. Even if the signal X and clock CK conflict with each other and the respective register circuits input wrong data, shift pulses are only shifted forward or backward by one step, which can easily be corrected in a next cycle.


Inventors:
Suzuki Higashi
Application Number:
JP27346499A
Publication Date:
September 14, 2005
Filing Date:
September 27, 1999
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
Toshiba Corporation
International Classes:
G11C19/00; G11C19/28; H03K23/54; H03K23/56; (IPC1-7): H03K23/54; G11C19/00; G11C19/28; H03K23/56
Domestic Patent References:
JP3236628A
JP10041803A
JP9261035A
JP9297998A
JP51102457A
JP49131674A
Attorney, Agent or Firm:
Kazuo Sato
Hidetoshi Tachibana
Yasukazu Sato
Yasushi Kawasaki