Title:
半導体回路
Document Type and Number:
Japanese Patent JP4996057
Kind Code:
B2
Abstract:
This invention includes a circuit ( 11 ) to be protected and an ESD protection circuit ( 2 ) which protects the circuit ( 11 ) to be protected against electrostatic discharge. The circuit ( 11 ) to be protected includes a bipolar transistor (TR 1 ), and the emitter of the bipolar transistor (TR 1 ) is connected to an external connection terminal ( 3 ). A current limiting element (Z) is provided between the collector of the bipolar transistor (TR 1 ) and a first power supply terminal ( 4 ). When a negative ESD pulse is applied to the external connection terminal ( 3 ) with respect to a power supply voltage of the first power supply terminal ( 4 ), the current limiting element (Z) limits the emitter current of the bipolar transistor (TR 1 ) and protects the transistor (TR 1 ) against any breakdown.
Inventors:
Coronel Aristotle Malai
Shinobu Saito
Shinobu Saito
Application Number:
JP2005119926A
Publication Date:
August 08, 2012
Filing Date:
April 18, 2005
Export Citation:
Assignee:
Asahi Kasei Electronics Co., Ltd.
International Classes:
H01L27/06; H01L21/822; H01L27/02; H01L27/04; H02H9/00
Domestic Patent References:
| JP8172162A | ||||
| JP3105962A | ||||
| JP6013554A | ||||
| JP9116100A | ||||
| JP10209292A | ||||
| JP7503599A | ||||
| JP5267584A | ||||
| JP9017961A |
Attorney, Agent or Firm:
Tetsuya Mori
Yoshiaki Naito
Hide Tanaka Tetsu
Yoshiaki Naito
Hide Tanaka Tetsu