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Title:
SEMICONDUCTOR DEFECT ANALYZING DEVICE AND DEFECT MODE CLASSIFYING METHOD USING THE SAME
Document Type and Number:
Japanese Patent JP2005190604
Kind Code:
A
Abstract:

To quicken the defect analysis of a semiconductor memory by automatically updating a defect mode criterion when the number of defects of the FMB data of the semiconductor memory is equal to or more than a threshold value.

This semiconductor defect analyzing device is provided with a measured data memory device 3 for obtaining and storing the FBM data of a semiconductor memory, and a CPU 1 having a creating means for creating the defect mode criterion of the semiconductor memory, a calculating means for classifying defect modes to calculate the characteristics of the defect modes based on the FBM data stored in the measured data memory device 3, and an updating means for updating the defect mode criterion when the amount of characteristics is compared with the defect mode to find that its ratio is equal to or more than the threshold value of the defect mode criterion.


Inventors:
KODAMA MASAMI
Application Number:
JP2003432242A
Publication Date:
July 14, 2005
Filing Date:
December 26, 2003
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G11C29/00; G11C29/44; H01L21/66; G01R31/28; (IPC1-7): G11C29/00; G01R31/28; H01L21/66
Attorney, Agent or Firm:
Hideaki Togawa