Title:
SEMICONDUCTOR DEVICE AND ARRANGING OF RESISTORS THEREOF
Document Type and Number:
Japanese Patent JP3147155
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce the effects of parasitic capacitance of a resistor and improve frequency characteristic in a higher region by forming dummy resistors according to a same process and a same size as a unit resistor to obtain a uniform potential for the dummy resistors, and by mounting the unit resistors and the dummy resistors on a substrate so that they are surrounded by the substrate to make potential of the substrate uniform.
SOLUTION: Two unit resistors R1, R2 identical in size manufactured by the same process are sandwiched between identical size dummy resistors 101-103 manufactured by the same process as for the resistors R1, R2 so that the resistors R1, R2 and the resistors 101-103 are arranged alternately. The dummy resistors 101-103 are connected together with wiring 106, so that they are at a predetermined uniform potential Vb1, and a substrate on which the unit resistors R1, R2 and the dummy resistors 101 and 103 are mounted, is kept at a predetermined uniform potential Vb2. Thus, a coupling due to the parasitic capacitance of the resistors can be reduced, and the frequency characteristic in the high region can be improved.
Inventors:
Hiroshi Nakamura
Yutaka Takahashi
Yutaka Takahashi
Application Number:
JP30878697A
Publication Date:
March 19, 2001
Filing Date:
November 11, 1997
Export Citation:
Assignee:
NEC
International Classes:
H01L27/04; H01L21/822; (IPC1-7): H01L27/04; H01L21/822
Domestic Patent References:
| JP5918670A | ||||
| JP563146A | ||||
| JP7147385A |
Attorney, Agent or Firm:
Nobuyuki Kaneda (2 others)