Title:
SEMICONDUCTOR DEVICE AND CELL
Document Type and Number:
Japanese Patent JP2005197518
Kind Code:
A
Abstract:
To provide a semiconductor device which suppresses variations of a power supply voltage and a ground voltage, reduces an area therefor, and hardly detours signal wiring.
A cell 100 comprises three wiring layers (gate electrode layer, source/drain electrode layer, terminal layer) on a semiconductor substrate with a transistor formed thereon. The wiring layer wherein an input terminal 151 and an output terminal 152 are formed for connection between cells, comprises a power supply wiring pass area 153 wherein power supply wiring can be passed. Power supply wiring for supplying the power supply voltage and the ground voltage from an external power source to the transistor in the cell is laid in the power supply wiring pass area 153.
Inventors:
KISHISHITA KEISUKE
Application Number:
JP2004003169A
Publication Date:
July 21, 2005
Filing Date:
January 08, 2004
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H01L21/822; H01L21/82; H01L27/02; H01L27/04; H01L27/118; H05B37/02; H01L27/105; (IPC1-7): H01L21/82; H01L21/822; H01L27/04; H01L27/118
Attorney, Agent or Firm:
Shiro Ogasawara