Title:
SEMICONDUCTOR DEVICE AND CIRCUIT SIMULATION METHOD
Document Type and Number:
Japanese Patent JP3962384
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To improve circuit simulation accuracy for propagation delay time and consumed power of a semiconductor integrated circuit, by making the accuracy of SPICE parameters improved by grasping accurate DC characteristics of a MOS transistor used in a CMOS logical circuit.
SOLUTION: In a present semiconductor device, there are provided a ring oscillator 22 and a monitor 7 on the same wafer (not shown). In the ring oscillator 22, two lines of a plurality of CMOS logical circuits (not shown) are disposed, and CMOS transistors of the one line among these two lines are disposed point-symmetric, with respect to the CMOS transistors of the other line. In the monitor 7, there are provided monitoring CMOS transistors 26a, 26b corresponding to each layout direction of the two lines of the CMOS logical circuits in the ring oscillator 22. Consequently, even the errors caused by different layout directions can be monitored.
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Inventors:
Yasuyuki Sahara
Application Number:
JP2004060337A
Publication Date:
August 22, 2007
Filing Date:
March 04, 2004
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G06F17/50; H01L21/822; H01L21/82; H01L27/04; (IPC1-7): H01L21/822; G06F17/50; H01L21/82; H01L27/04
Domestic Patent References:
| JP2003188689A | ||||
| JP2002270659A | ||||
| JP62190750A |
Attorney, Agent or Firm:
Hiroshi Maeda
Hiroshi Koyama
Hiroshi Takeuchi
Yuji Takeuchi
Katsumi Imae
Tomoo Harada
Hiroshi Koyama
Hiroshi Takeuchi
Yuji Takeuchi
Katsumi Imae
Tomoo Harada