To make a DLL circuit correctly lock even when a jitter component is superimposed on a clock signal.
A semiconductor device comprises a delay line 101 creating a clock signal LCLK depending on a count value of a counter part 102 and an inversion control part 103 controlling whether to invert the clock signal LCLK. The inversion control part 103 outputs the clock signal LCLK with or without inversion after resetting the count value of the counter part 102 to a first initial value. Subsequently, the inversion control part 103 resets the count value of the counter part 102 to a second initial value. According to the present invention, though the inversion control part 103 inverts the clock signal LCLK improperly or not inverts the clock signal LCLK improperly due to an influence of jitter and the like, down count (or up count) does not repeat multiple times. Accordingly, offset values can be used as the first and the second initial values.
Ogata Japanese
Yasuyuki Kurose
Takuya Mitani
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