Title:
半導体装置及び半導体メモリのデータ読出方法
Document Type and Number:
Japanese Patent JP7236574
Kind Code:
B2
Abstract:
PURPOSE: To provide a semiconductor device capable of properly reading data written in a memory cell regardless of variation in manufacture and a semiconductor memory data reading method.CONSTITUTION: A semiconductor device according to the present invention includes: a charge and discharge circuit which charges and discharges a main bit line connected to one of a plurality of memory cells; and a sense amplifier which amplifies a voltage generated in the main bit line by a current flowing to the main bit line following discharge to thereby generate a read signal. The charge and discharge circuit is inserted and arranged at different positions in a path of the main bit line, includes a plurality of switch elements which blocks the path when each in an OFF state and connects the path when it is in an ON state, sets, in an OFF state, one of the switch elements according to an adjustment signal included in the plurality of switch elements during the charging of the main bit line and sets the other switch element in an ON state, and then discharges electric charges at the main bit line by switching one of the switch elements to an ON state.SELECTED DRAWING: Figure 3
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Inventors:
Shuhei Kamano
Application Number:
JP2022026663A
Publication Date:
March 09, 2023
Filing Date:
February 24, 2022
Export Citation:
Assignee:
LAPIS Semiconductor Co., Ltd.
International Classes:
G11C16/24; G11C7/12
Domestic Patent References:
| JP2001167591A | ||||
| JP2011507139A |
Attorney, Agent or Firm:
Fujihiko Motohiko