Title:
SEMICONDUCTOR DEVICE AND DESIGN METHOD FOR THE SAME
Document Type and Number:
Japanese Patent JP2004145768
Kind Code:
A
Abstract:
To provide a semiconductor device capable of reducing a probability of erroneous operation of a circuit in proportion to delay fluctuation and a method for designing the device .
By minimizing an amount of timing error of a path between elements which are synchronized with reference to a clock signal in a process 102 by adjusting a delay time to the clock signal, a timing error deleting process 103 is simplified. After the deletion of the timing error in the process 103, in the process 104, a minimum slack value is maximized and, while the minimum slack value is being met, a sum of slack values of timing margin is maximized.
Inventors:
MATSUMURA YOICHI
OHASHI TAKAKO
YASUI TAKUYA
OHASHI TAKAKO
YASUI TAKUYA
Application Number:
JP2002311971A
Publication Date:
May 20, 2004
Filing Date:
October 28, 2002
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G06F17/50; H01L21/82; (IPC1-7): G06F17/50; H01L21/82
Attorney, Agent or Firm:
Yoshihiro Morimoto