Title:
半導体装置の設計方法および装置
Document Type and Number:
Japanese Patent JP4202079
Kind Code:
B2
Abstract:
To facilitate layout verification of a circuit in which an analog circuit and a digital circuit coexists.
Wiring as a possible noise source and wiring which is not noise-resistant are specified on a circuit diagram are indicated on a circuit, and an identification display means 11 identifies a pair of wiring patterns the parasitic capacity of which exceeds a specific value and displays it on the circuit diagram and a layout diagram when the parasitic capacity between the wiring patterns as the possible noise source and the wiring which is not noise-resistant is extracted.
COPYRIGHT: (C)2004,JPO
More Like This:
| JPS63226773 | AUTOMATIC WIRING METHOD |
| JP2000265569 | METHOD FOR DESIGNING BUILDING |
| JP3251263 | RETURN PATH CUT OFF CHECK SYSTEM FOR PRINTED BOARD |
Inventors:
Maruo Shoro
Mineo Nishimoto
Hiroaki Otake
Mineo Nishimoto
Hiroaki Otake
Application Number:
JP2002274644A
Publication Date:
December 24, 2008
Filing Date:
September 20, 2002
Export Citation:
Assignee:
Asahi Kasei Electronics Co., Ltd.
International Classes:
G06F17/50; H01L21/82; H01L21/822; H01L27/04
Domestic Patent References:
| JP2002259486A | ||||
| JP2000172727A | ||||
| JP11250111A | ||||
| JP2000113024A | ||||
| JP2001035925A | ||||
| JP2002183232A | ||||
| JP5210710A | ||||
| JP4054676A |
Attorney, Agent or Firm:
Tetsuya Mori
Yoshiaki Naito
Cui Shu Tetsu
Yoshiaki Naito
Cui Shu Tetsu