Title:
SEMICONDUCTOR DEVICE AND FABRICATION THEREOF
Document Type and Number:
Japanese Patent JPH08316348
Kind Code:
A
Abstract:
PURPOSE: To obtain an EEPROM in which increase of fluctuation in the coupling ratio can be suppressed among cells regardless of fine patterning.
CONSTITUTION: The semiconductor device comprises a floating gate electrode 15 formed on a p-type silicon substrate 11 through a gate insulation film 14, and a control gate 17 formed on the floating gate electrode 15 through an insulation film 16 between gate electrodes wherein the profile of the gate insulation film 14 and the insulation film 16 between gate electrodes at a part facing the floating gate electrode 15 is determined while being self-aligned.
Inventors:
SAIDA SHIGEHIKO
OZAWA YOSHIO
OZAWA YOSHIO
Application Number:
JP5195096A
Publication Date:
November 29, 1996
Filing Date:
March 08, 1996
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
H01L21/8247; H01L27/108; H01L27/115; H01L29/76; H01L29/78; H01L29/788; H01L29/792; H01L29/94; H01L31/119; (IPC1-7): H01L21/8247; H01L29/788; H01L29/792; H01L27/115; H01L29/78
Attorney, Agent or Firm:
Takehiko Suzue
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