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Title:
SEMICONDUCTOR DEVICE HAVING EEPROM AND MASK ROM AND ITS MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP2004080037
Kind Code:
A
Abstract:

To provide a semiconductor device having an EEPROM and a mask ROM, and a method for manufacturing the semiconductor device.

The method includes a step for forming an element separation film for limiting an active region on a semiconductor substrate before the formation of a gate insulating film on the region. A photoresist pattern is formed, where the photoresist pattern allows a specific region in the gate insulating film to expose on the semiconductor substrate containing the gate insulating film. After that, an ion implantation process for forming an impurity region and a gate insulating etching process for forming a tunnel insulating film are used as a mask used in common with the photoresist pattern for executing successively. The formed impurity region includes a floating impurity region and a channel impurity region. The gate insulating film etching process can recess the element separation film being exposed through the photoresist pattern. In the formed device, an upper surface where the element separation film at a portion being separated by the channel impurity region has a higher upper surface as compared with the element separation film at a portion adjacent to the channel impurity region.


Inventors:
PARK WEON-HO
Application Number:
JP2003293184A
Publication Date:
March 11, 2004
Filing Date:
August 13, 2003
Export Citation:
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Assignee:
SAMSUNG ELECTRONICS CO LTD
International Classes:
H01L27/088; H01L21/336; H01L21/8234; H01L21/8246; H01L21/8247; H01L27/10; H01L27/105; H01L27/112; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L21/8246; H01L21/8234; H01L21/8247; H01L27/088; H01L27/10; H01L27/112; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
JPH05145043A1993-06-11
JPH09148457A1997-06-06
Attorney, Agent or Firm:
Masatake Shiga
Takashi Watanabe