To suppress increase of a BIST circuit even when memory capacity of a memory part is increased, in a semiconductor device.

A circuit used when usual operation is performed is used also as a part of the BIST circuit, in the semiconductor device having a memory self-checking function. Expected values are stored in a data input latch 2 serving both as the data input latch of a memory used for usual operation and the data input latch of expected values of a test circuit, read data of the memory are stored in a data output latch 3 serving as both the output latch of the memory used for usual operation and the compared data latch. The semiconductor device has a comparator 4 comparing the output of the data input latch and the output of the data output latch with each other, a read/write control counter 5 generating read write mode switching signals by dividing a clock frequency, a means 14 reversing the data of the data input latch, and a means 8 making a refresh address counter serve also as the address generating counter of the test circuit.