Title:
SEMICONDUCTOR DEVICE HAVING MISFET CONTROL TYPE THYRISTOR
Document Type and Number:
Japanese Patent JP3163677
Kind Code:
B2
Abstract:
PURPOSE: To realize a semiconductor device capable of controlling high current by suppressing a discontinuity in voltage-current characteristics and generation of latch-up with high dielectric strength and low resistance of the whole device in a semiconductor device having a low ON-resistance MOS control type thyristor.
CONSTITUTION: A P-type first base layer 23, an N-type floating emitter layer 24, and a P-type second base layer 25 are succesively formed with high precision in an N- type base layer 14 by double diffusion method, thereby decreasing the resistance of MOS. Formation of a source layer 17 inside the second base layer 25 to restrict current flowing through the second base layer 25 allows a thyristor mode to be realized earlier and a parasitic thyristor to be prevented from making continuity.
Inventors:
Katsunori Ueno
Application Number:
JP24342991A
Publication Date:
May 08, 2001
Filing Date:
September 24, 1991
Export Citation:
Assignee:
Fuji Electric Co., Ltd.
International Classes:
H01L29/74; H01L29/10; H01L29/745; H01L29/749; (IPC1-7): H01L29/749
Domestic Patent References:
| JP4268766A | ||||
| JP2271672A | ||||
| JP2312275A |
Attorney, Agent or Firm:
Minoru Yamada