Title:
SEMICONDUCTOR DEVICE HAVING STRAINED SUPER
Document Type and Number:
Japanese Patent JP2707183
Kind Code:
B2
Abstract:
PURPOSE: To reduce the total stress, by laminating first semiconductor and second semiconductor which has lattice constants smaller than those of the first semiconductor on a clad layer having almost intermediate lattice constants between those of the first semiconductor and those of the second semiconductor.
CONSTITUTION: On an n-type InP substrate 1 the following are laminated; an n-type InP layer 2 as an n-type clad layer, an InGays well layer 11, an InGaAsP barrier layer 12, a p-type InP layer 3 as a p-type clad layer, and a p-type InGaAsP cap layer 4 for electrode contact. A buried stripe structure for lateral mode control and current constriction is formed by using a semiinsulative InP layer 5. The barrier layer 12 has lattice constants smaller than those of the well layer 11. The clad layers 2, 3 have almost intermediate lattice constants between those of the barrier layer 12 and those of the well layer 11. The barrier layers 12 and the well layers 11 are alternately laminated, and the barrier layers 12 are positioned as the uppermost layer and the lowest layer, thereby forming a strained super lattice.
Inventors:
Masashi Usami
Yuichi Matsushima
Yuichi Matsushima
Application Number:
JP8746592A
Publication Date:
January 28, 1998
Filing Date:
March 12, 1992
Export Citation:
Assignee:
International Telegraph and Telephone Corporation
International Classes:
G02F1/025; B82Y20/00; G02F1/313; H01L29/15; H01S5/00; (IPC1-7): H01S3/18
Domestic Patent References:
| JP4234184A | ||||
| JP321093A | ||||
| JP422185A | ||||
| JP6399589A |
Attorney, Agent or Firm:
Otsuka Manabu
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