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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE AND INPUT PIN CAPACITY SETTING METHOD
Document Type and Number:
Japanese Patent JP2004128363
Kind Code:
A
Abstract:

To solve the problem that using a semiconductor chip whose input pin capacitance is set for a single chip package to make up a multi-chip package causes an increase in capacity required for the input pins to exceed the upper limit of the spec (specifications and standards) of the input pins.

A semiconductor device is mounted with one or two of the semiconductor chips equipped with an input circuit including a wiring 3 for connecting an input pad 2 and an internal circuit, a first electrostatic protection element 1 (Pch-1, Nch-1) connected electrically with the wiring 3, a second electrostatic protection element 1 (Pch-2, Nch-2) arranged in the vicinity of the wiring 3, and a fuse 4 arranged between the wiring 3 and the second electrostatic protection element. In the case of one semiconductor chip, the wiring 3 and the second electrostatic protection element are connected electrically with each other by the fuse 4. In the case of two chips, the wiring 3 and the second electrostatic protection element are disconnected electrically with each other by cutting the fuse 4.


Inventors:
SASAHARA KATSUHIKO
Application Number:
JP2002293148A
Publication Date:
April 22, 2004
Filing Date:
October 07, 2002
Export Citation:
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Assignee:
OKI ELECTRIC IND CO LTD
International Classes:
H01L27/04; H01L21/82; H01L21/822; H01L23/60; H01L27/02; H01L29/00; (IPC1-7): H01L23/60; H01L21/82; H01L21/822; H01L27/04
Attorney, Agent or Firm:
Toshiaki Suzuki