To contract the inspection times of the respective analog macrocells (A/D converter and D/A converter macrocells) of a plurality of LSIs, by inspecting them concurrently, and to make possible the cutdowns of their inspection instruments, and to reduce the inspection cost.

On a semiconductor device, digital and analog macrocells are mounted, and as the analog macrocells, A/D converter and D/A converter macrocells 1, 3 are provided, and further, a test circuit 4 is provided additionally. The test circuit 4 is formed, to comprise registers where there are provided an index register portion for performing the assignment of a plurality of LSIs, a correction-bit oriented register portion for correcting the bit-number of the input and output of the respective analog macrocells, and a bit-number oriented register portion wherein the respective analog macrocells are decided, as to whether they are proper. By using a plurality of LSIs having such a constitution, the respective analog macrocells of the plurality of LSIs are inspected concurrently to realize shortening of the inspection times and to realize reduction in their inspection instruments and in the inspection cost.