半導体装置及びそのレイアウト作成方法

Title:

半導体装置及びそのレイアウト作成方法

Document Type and Number:

Japanese Patent JP5235936

Kind Code:

B2

Abstract:

A semiconductor device includes: a plurality of line features including at least one real feature which includes a gate electrode portion, and at least one dummy feature. Two of multiple ones of the dummy feature, and at least one of the line features interposed between the two dummy features and including the at least one real feature form parallel running line features which are evenly spaced. The parallel running line features have an identical width, and line end portions of the parallel running line features are substantially flush. Line end portion uniformization dummy features are formed on extensions of the line end portions of the parallel running line features. The line end portion uniformization dummy features include a plurality of linear features each having a same width as each of the line features and spaced at intervals equal to an interval between each adjacent pair of the line features.

Inventors:

Akio Misaka
Yasuko Tabata
Hideyuki Arai
Takajun Yamada

Application Number:

JP2010108285A

Publication Date:

July 10, 2013

Filing Date:

May 10, 2010

Export Citation:

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Assignee:

Panasonic Corporation

International Classes:

H01L21/82; G03F1/36; G03F1/68; G03F1/70; H01L21/822; H01L21/8238; H01L27/04; H01L27/092

Domestic Patent References:

JP2005072133A
JP2005167039A
JP2006332348A
JP2008235350A

Attorney, Agent or Firm:

Maeda patent office
Hiroshi Maeda
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Kazunari Ninomiya
Tomoo Harada
Iseki Katsumori
Seki Kei
Yasuya Sugiura
Daisuke Kawabe
Masanori Hasegawa
Tsuguya Iwashita
Koji Fukumoto
Ryo Maeda
Mawaki Hachizo
Yukichi Matsunaga
Kenji Kawakita
Shohei Okazawa

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