Title:
SEMICONDUCTOR DEVICE AND ITS MANUFACTURE
Document Type and Number:
Japanese Patent JP3299158
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To facilitate increase in operating speed and save power consumption at low cost in a subquarter micron range.
SOLUTION: Two MOS transistors, in each of which first and second gate electrodes 14A and 16A are arranged in parallel with each other, and a first n-type drain diffusion layer 19 on the first gate electrode 14A side is connected in series with a second n-type source diffusion layer 20 on the second gate electrode 16A side, are formed on a semiconductor substrate 11 composed of p-type silicon. In the semiconductor substrate 11, a first p-type diffusion layer 22 for controlling high-concentration threshold is formed in the source-side section of a channel region below the first gate electrode 14A on the first n-type source diffusion layer 19 side and, at the same time, a second p-type diffusion layer 23 for controlling high-concentration threshold is formed below the second gate electrode 16A on the second n-type source diffusion layer 20 side.
Inventors:
Akira Hiroki
Shinji Odanaka
Shinji Odanaka
Application Number:
JP35315797A
Publication Date:
July 08, 2002
Filing Date:
December 22, 1997
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H01L29/78; H01L21/265; H01L21/8238; H01L27/092; (IPC1-7): H01L21/8238; H01L21/265; H01L27/092; H01L29/78
Domestic Patent References:
| JP218960A | ||||
| JP464260A | ||||
| JP8153873A | ||||
| JP5982766A |
Attorney, Agent or Firm:
Hiroshi Maeda