Title:
SEMICONDUCTOR DEVICE AND ITS MANUFACTURE
Document Type and Number:
Japanese Patent JP3504025
Kind Code:
B2
Abstract:
PURPOSE: To prevent the formation of a parasitic transistor and the decline in threshold voltage by making the shape of a semiconductor layer a proper one after oxidization.
CONSTITUTION: On side faces of a semiconductor layer 3, side wall insulating films 30 with the width increased downward are formed. On the semiconductor layer 3 and the side wall insulating films 30, a gate electrode layer 5 is formed.
Inventors:
Toshiaki Iwamatsu
Yasuo Inoue
Yasuo Inoue
Application Number:
JP13944995A
Publication Date:
March 08, 2004
Filing Date:
June 06, 1995
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
H01L21/336; H01L21/762; H01L21/84; H01L27/12; H01L29/786; (IPC1-7): H01L29/786; H01L21/336; H01L21/762
Domestic Patent References:
| JP63288058A | ||||
| JP3169025A | ||||
| JP2103952A | ||||
| JP322567A | ||||
| JP5166919A |
Attorney, Agent or Firm:
Fukami Hisaro (5 others)