Title:
SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP3845272
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor device equipped with a high-reliability CMOIS.SRAM cell using an SOI substrate having more superior soft error resistance and its manufacturing method.
SOLUTION: This semiconductor device comprises a gate electrode formed on a surface semiconductor layer on the SOI substrate across a gate insulating film and 1st conduction type source/drain areas formed on the surface semiconductor layer on both the sides of the gate electrode and a 2nd conduction type lead-out diffusion layer is formed in contact with both or one of the 1st conduction type source/drain areas; and a silicide layer is formed from on at least the 1st conduction type source/drain area to on the 2nd conduction type lead-out diffusion layer and a ground potential is applied to the silicide layer.
Inventors:
Satoshi Aoki
Application Number:
JP2001185548A
Publication Date:
November 15, 2006
Filing Date:
June 19, 2001
Export Citation:
Assignee:
Sharp Corporation
International Classes:
H01L27/08; H01L21/8238; H01L21/8244; H01L21/84; H01L27/092; H01L27/11; H01L27/12; H01L29/786; (IPC1-7): H01L29/786; H01L21/8238; H01L21/8244; H01L27/08; H01L27/092; H01L27/11
Domestic Patent References:
| JP2000332250A | ||||
| JP62109355A | ||||
| JP2000269509A | ||||
| JP11040811A | ||||
| JP2000022160A |
Attorney, Agent or Firm:
Shintaro Nogawa