Title:
SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP3910973
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor device including multilayer metalization construction by which an increase in line capacity is suppressed, and a problem of deterioration of leak characteristics between interconnections is avoided; and to provide its manufacturing method.
SOLUTION: The semiconductor device comprises interconnections 117, 127, 137, conductive films 118, 128, 138 which prevent diffusion of wiring materials formed on the surface of an upper side of the interconnections, and insulating films of a lower dielectric constant, 111, 121, 131, 141 which are laminated to form at least two layers. Boundary surfaces include the insulating films positioned at side faces of the interconnections.
Inventors:
Tsumura Ichido
Takako Usui
Takako Usui
Application Number:
JP2004126980A
Publication Date:
April 25, 2007
Filing Date:
April 22, 2004
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L21/3205; H01L21/768; H01L23/48; H01L23/52; H01L23/522; H01L23/532; (IPC1-7): H01L21/3205; H01L21/768
Domestic Patent References:
| JP2003332422A | ||||
| JP2001284453A | ||||
| JP11354638A | ||||
| JP2002151518A | ||||
| JP2000323479A |
Attorney, Agent or Firm:
Takehiko Suzue
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Sadao Muramatsu
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Sadao Muramatsu
Ryo Hashimoto