To provide a semiconductor device and its self test method in which test time is reduced.
The semiconductor device is provided with a serial interface 11 which operates in a self test mode, reading means 12 and 14 which read a prestored self test program, a means 14 which decodes the read self test program, means 15, 17, 18 and 19 which control writing, erasure and reading in accordance with a decoded result, the means 14, 15 and 19 which determine whether the writing or the erasure is normally performed or not, means 14, 15, 17 and 23 which replace a failed cell with a redundant cell 21, the means 14, 15, 17, 18 and 19 which perform re-test of the replaced redundant cell, a volatile first storage means 24 which stores failed address information being replaced to the redundant cell and a nonvolatile second storage means 25 which stores test information and the failed address information stored in the first storage means.
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto
Next Patent: SEMICONDUCTOR MEMORY