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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF AND IMAGE DISPLAY DEVICE
Document Type and Number:
Japanese Patent JPH1145999
Kind Code:
A
Abstract:

To relax an electric field on the drain side, to inhibit generation of avalanche breakdown and hot carriers and to increase breakdown strength and lower a leakage current, by forming conductive side walls onto both end faces of a gate electrode, and composing a second conductor on the source side and a third conductor on the drain side of the side walls.

Since conductive side walls (a second conductor on the source side and a third conductor on the drain side) 50 slightly extended on high- concentration impurity regions 4, 5, while being crossed over low-concentration impurity regions 14, 15, are formed of polycrystalline silicon films and brought to a connected state with a gate electrode 18, the side walls 50 substantially function as gate electrodes. Since the side walls 50 on both end sides of a first conductor are formed in the conductors, the ends of the gate electrode 18 are formed extending (overlap) up to the low-concentration drain region 14 and the low-concentration source region 15, because the gate electrodes are composed substantially of the first conductor (the gate electrode 18) and the side walls on both sides of the first conductor. Accordingly, an electric field in the vicinity of a drain is relaxed.


Inventors:
Hatano, Mutsuko
Akimoto, Hajime
Nakahara, Hitoshi
Application Number:
JP1997000198034
Publication Date:
February 16, 1999
Filing Date:
July 24, 1997
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L21/336; H01L29/78; H01L29/786; (IPC1-7): H01L29/786; H01L21/336; H01L29/78
Attorney, Agent or Firm:
秋田 収喜