Title:
SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JP3420706
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To improve wiring efficiency and to cope with the shrinking of a semiconductor element and the narrow pitching of a ball pitch by reducing the plate leader line of a substrate and the area for the line in the semiconductor device, wherein a circuit substrate is stuck to the functional surface of the semiconductor element and connected through a wire.
SOLUTION: A plate leader line G is formed in a region (shaded section), corresponding to the center pad of the semiconductor element of a circuit substrate 4a. After electrolytic plating is performed using this line G, this part is removed together with the leader line. Then, the device is struck to a semiconductor chip, and the substrate and the semiconductor chip are connected through wire bonding. Furthermore, in the case of the semiconductor device, to which the lead extending from the circuit pattern of the substrate is connected, the tip part of the lead is connected by the conducting connecting piece for plating and is connected to the circuit pattern, and plating is performed. After only the insulating film at this part is removed, the device is stuck to the semiconductor chip. While the tip of the lead is being cut from conductive connecting piece, the lead is connected to the semiconductor chip.
Inventors:
Sato Tomoe
Jun Ohmori
Jun Ohmori
Application Number:
JP26857098A
Publication Date:
June 30, 2003
Filing Date:
September 22, 1998
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L23/12; H01L21/60; H01L23/498; H05K3/00; H05K3/24; H01L23/13; H05K1/00; (IPC1-7): H01L23/12; H01L21/60
Domestic Patent References:
| JP737931A | ||||
| JP5259214A | ||||
| JP9260535A | ||||
| JP11233566A |
Attorney, Agent or Firm:
Saichi Suyama