Title:
SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JP3458487
Kind Code:
B2
Abstract:
PURPOSE: To provide a technique for protecting the peripheral part of an upper electrode (control gate or the like) over a lower electrode (floating gate or the like) against damage caused by dry etching when the upper electrode is patterned by dry etching and for restraining the upper electrode from decreasing in thickness.
CONSTITUTION: A semiconductor device is provided with two or more laminated electrode structures equipped with at least an upper electrode 15 (control gate or the like serving as an upper electrode) and a lower electrode 14 (floating gate or the like serving as a lower electrode), wherein at least either of the electrodes is buried in a groove 11.
Inventors:
Hirofumi Sumi
Application Number:
JP26201594A
Publication Date:
October 20, 2003
Filing Date:
September 30, 1994
Export Citation:
Assignee:
ソニー株式会社
International Classes:
H01L21/8247; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP1225364A | ||||
| JP60154672A | ||||
| JP3198377A | ||||
| JP684938A | ||||
| JP6267943A | ||||
| JP4264728A |
Attorney, Agent or Firm:
Toru Takatsuki
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