Title:
SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JPH1154748
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To obtain a semiconductor device whose ON voltage is low and latch-up resistance is high. SOLUTION: A row of gate grooves 8 is provided to an N-type silicon layer (SOI layer) 3 so as to divide a P-type base layer 4 and an N-type emitter layer 5. The gate grooves 8 are provided extending from the N-type emitter layer 5 to a collector electrode 21. A gate electrode 1 is buried inside the gate groove 8 through the intermediary of a gate insulating film 9. A gate electrode 10 confronts the longitudinal section of a P-type base layer 4, so that a channel is kept wide. The wide region of the N-type silicon layer 3 confronting the gate groove 8 functions as a hole storage layer. As a result, a semiconductor device of this constitution can be lessened in ON voltage.
Inventors:
NOBUTO SHINJI
WATABE KIYOTO
TAKAHASHI HIDEKI
WATABE KIYOTO
TAKAHASHI HIDEKI
Application Number:
JP20917397A
Publication Date:
February 26, 1999
Filing Date:
August 04, 1997
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L29/739; H01L29/78; H01L29/786; H01L29/06; H01L29/423; (IPC1-7): H01L29/78; H01L29/786
Attorney, Agent or Firm:
Shigeaki Yoshida (2 outside)