PURPOSE: To reduce the period (TAT) from the receipt of an order for a channel implantation type ROM and the completion of the order by a method wherein the insulating film on a gate electrode is made thinner than the other regions.
CONSTITUTION: After source and drain regions 3 and 4, a gate oxide film, a gate electrode 6, and an SiO2 film 10 have been formed on a P-type Si substrate 1, a phosphorus glass layer 12 is deposited, the glass layer on the gate electrode 6 is thinned off by performing an etching, and a window 14 is formed. Then, a contact hole 9 and a wiring layer 8 are formed. Subsequently, a photoresist 13 is coated, a patterning is performed so that the specific part of the window 14 will be exposed, an ion implantation is conducted, and information is written in by changing the threshold voltage of the specific memory well. Consequently, as the writing-in of information can be performed after formation of the wiring layer, the TAT of a channel-implantation type ROM can be reduced, Also, as the gate electrode 6 is not exposed, the reliability of the title semiconductor device can be enhanced.
YOU SEIHATSU
MISAWA YASUMASA
YAMAUCHI KAZUMI
IWAMORI TOSHIMICHI
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