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Title:
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
Document Type and Number:
Japanese Patent JP2012182478
Kind Code:
A
Abstract:

To provide a semiconductor device which suppresses body floating effect, and to provide a manufacturing method of the semiconductor device.

A semiconductor device having a silicon on insulator (SOI) structure includes: a silicon substrate 1; an embedded insulation layer 2 formed on the silicon substrate 1; and a semiconductor layer 3 formed on the embedded insulation layer 2. The semiconductor layer 3 has a first conductive type body region 4, a second conductive type source region 5, and a second conductive type drain region 6, and a gate electrode 8 is formed on the body region 4 between the source region 5 and the drain region 6 via a gate oxide film 7. The source region 5 includes a second conductive type extension layer 52 and a silicide layer 51 contacting with the extension layer 52 at a side surface. A crystal defect region 12 is formed in a region of a depletion layer occurring in a boundary portion between the silicide layer 51 and the body region 4.


Inventors:
MAEKAWA SHIGETO
IPPOSHI TAKASHI
Application Number:
JP2012105298A
Publication Date:
September 20, 2012
Filing Date:
May 02, 2012
Export Citation:
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Assignee:
RENESAS ELECTRONICS CORP
International Classes:
H01L29/786; H01L21/28; H01L21/336; H01L21/8244; H01L27/11; H01L29/417
Domestic Patent References:
JP2003332579A2003-11-21
JP2000269503A2000-09-29
JP2004273589A2004-09-30
JP2006505131A2006-02-09
JP2001267576A2001-09-28
JP2000223713A2000-08-11
JP2004079748A2004-03-11
JP2004273589A2004-09-30
JP2003332579A2003-11-21
JP2000269503A2000-09-29
JP2006505131A2006-02-09
Foreign References:
WO2004040655A22004-05-13
WO2004040655A22004-05-13
Attorney, Agent or Firm:
吉竹 英俊
有田 貴弘