Title:
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
Document Type and Number:
Japanese Patent JP2016009808
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To inhibit an unintended increase in threshold voltage associated with a narrow channel of a MISFET to promote refinement and high breakdown voltage of the MISFET.SOLUTION: A semiconductor device comprises a p-type channel stopper region 18 for inversion prevention which is formed on a lower part of an element isolation trench 11 and formed in a manner such that an end project toward a channel region on a lower part of a gate oxide film 15 but which does not reach the channel region and off-set with respect to an end (an end of the element isolation trench 11) of the channel region. With this composition, diffusion of an impurity of the p-type channel stopper region 18 in a lateral direction (channel region direction) is inhibited and a decrease in carrier concentration at the end of the channel region is inhibited. Accordingly, a local increase in threshold voltage is suppressed.
Inventors:
TOMIOKA MASAHIRO
Application Number:
JP2014130823A
Publication Date:
January 18, 2016
Filing Date:
June 25, 2014
Export Citation:
Assignee:
RENESAS ELECTRONICS CORP
International Classes:
H01L21/336; H01L21/76; H01L29/78
Attorney, Agent or Firm:
Yamato Tsutsui
Atsushi Sugada
Akiko Tsutsui
Tetsuya Sakaji
Atsushi Sugada
Akiko Tsutsui
Tetsuya Sakaji
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