Title:
半導体装置製造方法および半導体装置
Document Type and Number:
Japanese Patent JP7143182
Kind Code:
B2
Abstract:
To provide a semiconductor device manufacturing method and a semiconductor device which are suitable for achieving a multilayered semiconductor element.SOLUTION: A semiconductor device manufacturing method of the present invention includes steps of: preparing a wafer 11 and a reinforcement wafer 12R having a laminated structure of a wafer 12/a temporary adhesive layer 13/a support substrate S; bonding the wafer 12 of the reinforcement wafer 12R to a surface 11a of the wafer 11 through an adhesive layer 21; forming a resin layer 31 on a surface 11b of the wafer 11; and detaching the support substrate S from the reinforcement wafer 12R that has been subjected to the step of bonding. A semiconductor device of the present invention has a laminated structure including wafers 11, 12, an adhesive layer 21 and a resin layer 31. The wafer 11 has surfaces 11a, 11b. The wafer 12 is located on a surface 11a side of the wafer 11 and is thinner than the wafer 11. The adhesive layer 21 is interposed between the wafers 11, 12. The resin layer 31 is in close contact with the surface 11b of the wafer 11.SELECTED DRAWING: Figure 1
Inventors:
Akira Yamakawa
Application Number:
JP2018199007A
Publication Date:
September 28, 2022
Filing Date:
October 23, 2018
Export Citation:
Assignee:
Daicel Corporation
International Classes:
H01L21/02; B32B37/00; H01L21/304
Domestic Patent References:
| JP2014013801A | ||||
| JP2001085453A | ||||
| JP2312220A |
Foreign References:
| WO2018075444A1 | ||||
| WO2018083961A1 |
Attorney, Agent or Firm:
Patent Attorney Corporation G-chemical