Title:
半導体装置の製造方法および半導体装置
Document Type and Number:
Japanese Patent JP7410898
Kind Code:
B2
Abstract:
Problem: To reduce the likelihood of insufficient electrical continuity in wiring in a semiconductor device. Solution: A method for manufacturing a semiconductor device includes placing, on a substrate surface, a first semiconductor element having a first surface on which a first pillar electrode is formed, via a surface opposite to the first surface, sealing a substrate-side pillar electrode and the first pillar electrode with a first sealant, removing a part of the first sealant to expose an end of the substrate-side pillar electrode and an end of the first pillar electrode, forming, on the first sealant, a plating layer electrically connected to the substrate-side pillar electrode and the first pillar electrode by plating, removing a part of the plating layer to form a residual plating layer, coupling a second semiconductor element onto the residual plating layer or a metal layer or a wiring layer formed on the residual plating layer, and sealing the residual plating layer and the second semiconductor element using a second sealant such that the first sealant is in contact with the second sealant.
Inventors:
Takashi Suzuki
Application Number:
JP2021039205A
Publication Date:
January 10, 2024
Filing Date:
March 11, 2021
Export Citation:
Assignee:
Aoi Electronics Co., Ltd.
International Classes:
H01L23/12; H01L25/065; H01L25/07; H01L25/18
Domestic Patent References:
| JP2012109297A |
Foreign References:
| WO2019240901A1 |
Attorney, Agent or Firm:
Asako Sudo
Akinobu Sudo
Akinobu Sudo
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