SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREFOR, AND MOUNTING STRUCTURE THEREOF

Title:

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREFOR, AND MOUNTING STRUCTURE THEREOF

Document Type and Number:

Japanese Patent JP3939504

Kind Code:

B2

Abstract:

PROBLEM TO BE SOLVED: To provide a semiconductor device in which passive elements, such as an antenna element, capacitive elements, etc., can be loaded in a chip, and to provide a method of manufacturing the device.
SOLUTION: An inverted F-type antenna is formed by providing a ground plane GP composed of a conductor layer 5-1 connected to a grounding pad 2A, a post 6A formed in a state where the post 6A is connected to the plane GP, another post 6B formed in a state where the post 6B is connected to a feeding pad 2B, and an upper conductor layer 8 which is formed on a sealing film 7 and arranged at a position where the layer 8 faces the conductor layer 5-1 in a state-where the layer 8 is connected to the posts 6A and 6B. Consequently, the antenna can be loaded in the chip. In addition, the capacitive elements Cp and Cp' can be constituted of upper conductor layers 12 connected to a conductor-plate wiring board and conductor layers 5-2 facing each other via the sealing film 7 or a dielectric film 13. Therefore, the capacitive elements CP and CP' can be loaded in the chip.

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Inventors:

Yoshitaka Aoki

Application Number:

JP2001118242A

Publication Date:

July 04, 2007

Filing Date:

April 17, 2001

Export Citation:

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Assignee:

CASIO COMPUTER CO.,LTD.
Oki Electric Industry Co., Ltd.

International Classes:

H01L23/12; H01L21/56; H01L21/60; H01L21/822; H01L23/31; H01L23/522; H01L25/00; H01L27/04; H01P11/00; H01Q1/38; H01Q13/08; (IPC1-7): H01L25/00; H01L21/56; H01L21/822; H01L23/12; H01L27/04; H01P11/00; H01Q1/38; H01Q13/08

Domestic Patent References:

JP5095082A
JP8330313A
JP10041632A
JP11046114A
JP11251755A
JP2000208944A
JP2000357757A
JP2001102861A
JP2002093945A
JP2002312747A

Attorney, Agent or Firm:

Hidemi Kashima

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