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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Document Type and Number:
Japanese Patent JP2004319632
Kind Code:
A
Abstract:

To provide a method of manufacturing a semiconductor device which can conduct stress relaxation at trench corners without reducing the area of an active region or the transistor width or stably form the resistance of a semiconductor substrate or a well of opposite conductivity type from that of the semiconductor substrate, in element isolation using an STI (shallow trench isolation) method.

Oxygen ions are implanted into an internal region 16 of a semiconductor substrate 11 containing a bottom 22 of a shallow groove 15 prior to forming the shallow groove 15 in an element isolation region 18 of the semiconductor substrate 11, and annealing is performed in a non-oxidizing atmosphere such as a nitride atmosphere or a vacuum atmosphere after forming the shallow groove 15 in the semiconductor substrate 11.


Inventors:
SAJIMA KAZUNORI
Application Number:
JP2003109254A
Publication Date:
November 11, 2004
Filing Date:
April 14, 2003
Export Citation:
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Assignee:
SHARP KK
International Classes:
H01L21/76; H01L21/265; (IPC1-7): H01L21/76; H01L21/265
Attorney, Agent or Firm:
Yoshifumi Masaki
Kaoru Hashimoto