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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP2001093908
Kind Code:
A
Abstract:

To provide a semiconductor device which has a small element area and can suppress damages caused by wire bonding, and a method for manufactur ing the device.

In a semiconductor device, an n+-type drain diffusion areas 4 which is formed as an impurity diffusion layer is formed in the n-type silicon layer (silicon active layer) of an SOI substrate constituted by forming the silicon layer 3 on a single-crystal silicon substrate 1 through a silicon oxide insulating layer 2. The surface-side part of the portion overlapping the diffusion area 4 of a drain electrode 7 constituting metallic wiring becomes a drain pad 17 serving as a bonding pad. An impact relieving section 9 composed of a silicon oxide film is provided between the drain pad 17 and the diffusion area 4 so as to relieve the impact given to the diffusion area 4 at the time of performing wire bonding. The impact relieving section 9 is formed on the portion overlapping the drain pad 17 of the diffusion area 4.


Inventors:
OGIWARA ATSUSHI
OKA NAOMASA
Application Number:
JP27152299A
Publication Date:
April 06, 2001
Filing Date:
September 27, 1999
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC WORKS LTD
International Classes:
H01L23/52; H01L21/3205; H01L21/60; (IPC1-7): H01L21/3205
Attorney, Agent or Firm:
Keisei Nishikawa (1 person outside)