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Title:
SEMICONDUCTOR DEVICE MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP2013004603
Kind Code:
A
Abstract:

To provide a semiconductor device manufacturing method capable of forming a gate electrode of a designed shape and size.

A semiconductor device manufacturing method according to a present embodiment comprises: forming laminates 17, 18 in which titanium layers 17a, 18a, aluminum layers 17b, 18b, nickel layers 17c, 18c and gold layers 17d, 18d are respectively laminated in this order on a surface of a semiconductor layer 12 at locations at a distance from each other; heating the laminates at a temperature higher than a melting point of aluminum to form a plurality of metal bodies 17', 18'; concurrently, forming ohmic contacts between the plurality of metal bodies 17', 18' and the semiconductor layer 12; subsequently, thinning the plurality of metal bodies 17', 18' to form a plurality of alloy layers 13a, 14a; forming a drain electrode 13 and a source electrode 14 respectively including the alloy layers 13a, 14a; subsequently, forming an opening 20 in a resist layer 19 between the drain electrode 13 and the source electrode 14; and forming a gate electrode 15 in the opening 20.


Inventors:
MATSUSHITA KEIICHI
Application Number:
JP2011132125A
Publication Date:
January 07, 2013
Filing Date:
June 14, 2011
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H01L21/338; H01L21/205; H01L21/28; H01L29/417; H01L29/778; H01L29/812
Attorney, Agent or Firm:
Amagi International Patent Office