Title:
SEMICONDUCTOR DEVICE MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP3165061
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent depletion of gate electrodes and impurities implanted during self-alignment from punching through the gate electrodes, with less by number of process steps.
SOLUTION: This method consists of a step for forming two-layer structure gate electrodes 7 and 8, each consisting of an n-type silicon film and a nitride film, on an n-wall 3 and p-wall 4, respectively, a step of covering the p-well 4 side with a photoresist 9 and then implanting ions using the two-layer structure gate electrode 7 on the n-wall 3 as a mask to thereby form an n-type diffused layer, a step of removing the photoresist 9 and removing the nitride films or oxide films of the two-layer structure gate electrodes 7 and 8 to thereby provide single layer structure gate electrodes 7 and 8, and a step of covering the n-well 3 side with a photoresist 12 and then implanting ions using the single- layer gate electrode on the p-well 4 as a mask to thereby form a p-type diffused layer and, at the same time, turn the single-layer structure gate electrode into a p-type electrode (or form a p+-type gate electrode 14).
Inventors:
Atsushi Tsuboi
Application Number:
JP8054697A
Publication Date:
May 14, 2001
Filing Date:
March 31, 1997
Export Citation:
Assignee:
NEC
International Classes:
H01L27/092; H01L21/8238; (IPC1-7): H01L21/8238; H01L27/092
Domestic Patent References:
| JP6430256A | ||||
| JP6269666A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)