Title:
SEMICONDUCTOR DEVICE, SEMICONDUCTOR MEMORY, AND TEST MODE ENTRY METHOD
Document Type and Number:
Japanese Patent JP3971078
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor memory in which erroneous entry for a test mode at the time of ordinary use can be surely prevented and various operation tests can be surely performed at the time of shipping.
SOLUTION: A test mode control section operating internal circuits 3 and 6 with a test mode based on a test mode command is provided with first control sections 4 and 8 non-activating at least one part of the internal circuits 3 and 6 and disabling input/output of data based on a test mode command, and a second control section 4a activating the internal circuit non-activated by the test mode command based on a releasing command inputted succeeding to the test mode command, and enabling input/output of data in a test mode.
Inventors:
Ito Shigema
Application Number:
JP2000049781A
Publication Date:
September 05, 2007
Filing Date:
February 25, 2000
Export Citation:
Assignee:
富士通株式会社
International Classes:
G01R31/28; G01R31/3185; G11C29/14; G11C11/401; G11C11/407; G11C29/00; G11C29/46; (IPC1-7): G11C29/00; G01R31/28; G01R31/3185; G11C11/407; G11C11/401
Domestic Patent References:
| JP2582518B2 | ||||
| JP2001242226A | ||||
| JP7229951A | ||||
| JP6300823A | ||||
| JP7192496A | ||||
| JP8086836A | ||||
| JP11086599A | ||||
| JP9223400A | ||||
| JP7029396A | ||||
| JP10332797A | ||||
| JP2000011696A |
Attorney, Agent or Firm:
Hironobu Onda
Makoto Onda
Makoto Onda