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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE AND METHOD OF EVALUATING THE SAME
Document Type and Number:
Japanese Patent JPH05326662
Kind Code:
A
Abstract:

PURPOSE: To evaluate a plurality of contacts at a wafer level simultaneously in terms of an EM durability evaluation and to further shorten an evaluating time under a high stress.

CONSTITUTION: An Al wiring layer 21 of a multilayer structure of an AlSi-Cu layer/TiN layer/Ti layer is called 'barrier metal'. An n-type semiconductor layer 22 is an active region in which a current flows. A p-type element isolation layer 23 is electrically isolated from an adjacent element formed at a predetermined position of a semiconductor substrate. An interlayer insulating film is provided with an opening for bringing the layers 21, 22 into contact with the layer 23. Sixteen contacts 24 are provided due to reliability of life evaluation of the contacts 24. A first terminal 25 includes the contact 24 of the layer 21 with the layer 22, a second terminal 26 includes the contact of the layer 21 with the layer 22, and a third terminal 27 includes the contact 24 of the layer 21 with the layer 23.


Inventors:
KAWAHARA HIROYUKI
Application Number:
JP12718992A
Publication Date:
December 10, 1993
Filing Date:
May 20, 1992
Export Citation:
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Assignee:
MATSUSHITA ELECTRONICS CORP
International Classes:
H01L21/66; (IPC1-7): H01L21/66
Attorney, Agent or Firm:
Akira Kobiji (2 outside)