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Title:
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Document Type and Number:
Japanese Patent JP2011066151
Kind Code:
A
Abstract:

To reduce parasitic resistance in a semiconductor device having a transistor of a GAA (Gate All Around) structure.

The semiconductor device includes: a semiconductor substrate 10; a first semiconductor layer 11 formed in source/drain regions on the semiconductor substrate; a second semiconductor layer 12 having a first part 12a formed on the first semiconductor layer and a second part 12b formed in a channel region positioned between the source/drain regions; a third semiconductor layer 13 formed on the first part of the second semiconductor layer; a gate electrode 22 formed around the second part of the second semiconductor layer via an insulating film 21; and contact plugs 31 formed in the first semiconductor layer, the first part of the second semiconductor layer and the third semiconductor layer. The diameter of the contact plug in the second semiconductor layer is smaller than those of the contact plugs in the first semiconductor layer and the third semiconductor layer.


Inventors:
IWAYAMA MASAYOSHI
KAJIYAMA TAKESHI
ASAO YOSHIAKI
Application Number:
JP2009000214808
Publication Date:
March 31, 2011
Filing Date:
September 16, 2009
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H01L29/78; H01L21/336; H01L29/06; H01L29/417; H01L29/786
Domestic Patent References:
JP2006270107A2006-10-05
JP2008543103A2008-11-27
JP2006352125A2006-12-28
JP2006080519A2006-03-23
JP2008544558A2008-12-04
Attorney, Agent or Firm:
蔵田 昌俊
河野 哲
中村 誠
福原 淑弘
峰 隆司
白根 俊郎
村松 貞男
野河 信久
幸長 保次郎
河野 直樹
砂川 克
勝村 紘
河井 将次
佐藤 立志
岡田 貴志
堀内 美保子
竹内 将訓
市原 卓三
山下 元