To improve breakdown capabilities of a power MOS transistor having a three-dimensional structure and an IGBT.
In a semiconductor device, a trench 21 is provided on an N+ substrate 1, and an N layer 2, an N- layer 3, a P layer 4, and an N+ layer 5 are stacked in the trench 21 so as to cover the trench 21. In the N+ layer 5, a trench 22 is provided such that a portion thereof penetrates through the N+ layer 5 to expose a surface of the P layer 4 in the vertical direction of the N+ substrate 1 and a portion thereof penetrates through the N+ layer 5 to expose a side surface of the P layer 4 in the horizontal direction of the N+ substrate 1. In the trench 22, a P+ layer 6 is provided so as to cover the trench 22. Trenches 23 are provided which penetrate through the N+ layer 5 to expose the surface of the P layer 4 in the vertical direction of the N+ substrate 1 and penetrate through the P layer 4 to expose a side surface of the N- layer 3 at one end and to expose a side surface of the N+ layer 5 at the other end in the horizontal direction of the N+ substrate 1, and are disposed between the P+ layer 6 and spaced apart from the side surfaces of the P+ layer 6. Trench gates 11 are provided so as to cover the trenches 23.
Fujiwara Yasutaka
Hajime Yamashita