Title:
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Document Type and Number:
Japanese Patent JP2015070078
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide an element isolation structure, having excellent area efficiency, of a semiconductor device comprising two semiconductor regions.SOLUTION: A semiconductor device 100A comprises: two p-type semiconductor regions 103 and 104; a lead-out region 121; and a deep trench insulating layer 112. The p-type semiconductor regions 103 and 104 are surrounded by the deep trench insulating layer 112. The lead-out region 121 separates the p-type semiconductor regions 103 and 104 in the deep trench insulating layer. The p-type semiconductor regions 103 and 104 are formed so as to be in contact with the deep trench insulating layer 112.
Inventors:
TSURUTA JUNJI
FUJII HIROMOTO
FUJII HIROMOTO
Application Number:
JP2013202302A
Publication Date:
April 13, 2015
Filing Date:
September 27, 2013
Export Citation:
Assignee:
RENESAS ELECTRONICS CORP
International Classes:
H01L21/76; H01L21/331; H01L21/761; H01L21/822; H01L27/04; H01L27/06; H01L27/08; H01L29/732; H01L29/74
Attorney, Agent or Firm:
Minoru Kudo