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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE
Document Type and Number:
Japanese Patent JP2001196534
Kind Code:
A
Abstract:

To prevent short-circuiting between solder bumps, even if the diameter of a solder bump at a solder junction is enlarged by preventing breakdown due to thermal fatigue of a solder junction.

An opening 12 on a substrate 11 is provided with a pair of IC packages 17 and has a plurality of straight leads 19 extending in transverse direction. An IC package mounting land 13, to be connected corresponding to a straight lead, is arranged in the upper and lower surfaces of a substrate and an external connection land as an external connection terminal is arranged on an extension line, where each straight lead is led out and is connected corresponding to the straight lead. An external connection land is constituted of an external connection land 14a of a first group, arranged at an integrated circuit package side and an external connection land 14b of a second group arranged outside the first group external connection land, and the first group external connection land and the second group external connection land are arranged in staggered manner.


Inventors:
KASATANI TAIJI
Application Number:
JP2000003417A
Publication Date:
July 19, 2001
Filing Date:
January 12, 2000
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L25/18; H01L21/60; H01L25/10; H01L25/11; H05K1/11; H05K1/14; H05K1/18; H05K3/34; (IPC1-7): H01L25/10; H01L25/11; H01L25/18; H01L21/60
Attorney, Agent or Firm:
Kaneo Miyata (1 person outside)