Title:
SEMICONDUCTOR DEVICE AND PATTERN ARRANGING METHOD THEREOF
Document Type and Number:
Japanese Patent JP3311243
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To improve a metal wiring pattern so as not to make photoresist foam, even if a cavity is generated in a protective film in a space between the metal wirings of a semiconductor device.
SOLUTION: Metal wirings 11 to 15 are arranged in parallel, and a first and a second passivation film, 16 and 17, are formed on the metal wirings 11 to 15 to serve as surface protective films. The adjacent wirings of the metal wirings 12 to 15 are narrow in inter-wiring space, so that the adjacent passivation films overlap each other to form straw-shaped voids 18 to 20. On the other hand, the metal wirings 11 and 12 are set large with respect to the inter-wiring space, so that the passivation films on the wirings 11 and 12 are separated from each other to form a loophole 21.
Inventors:
Makoto Irie
Takahiro Sato
Takahiro Sato
Application Number:
JP18579496A
Publication Date:
August 05, 2002
Filing Date:
July 16, 1996
Export Citation:
Assignee:
Toshiba Microelectronics Corporation
Toshiba Corporation
Toshiba Corporation
International Classes:
H01L21/82; H01L21/822; H01L23/52; H01L23/528; H01L21/3205; H01L27/04; (IPC1-7): H01L21/3205; H01L21/82; H01L21/822; H01L27/04
Domestic Patent References:
| JP3236239A | ||||
| JP3183135A | ||||
| JP945686A |
Attorney, Agent or Firm:
Kazuo Sato (3 others)