Title:
半導体デバイスの保護回路および方法
Document Type and Number:
Japanese Patent JP4421073
Kind Code:
B2
Abstract:
An electrostatic discharge (ESD) protection circuit (20) includes an active load circuit (22) connected to a Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor (21) having a Lightly Doped Drain (LDD). The active load circuit includes a current limiting circuit (26) and a load transistor (27). The ESD protection circuit (20) operates to protect a power transistor (16) from damage due to an electrostatic charge. During an ESD event, the LDMOS transistor (21) enters avalanche breakdown after the voltage of the electrostatic charge exceeds the breakdown voltage of the LDMOS transistor (21). The ESD protection circuit (20) provides a low resistance path during an ESD event to dissipate the electrostatic charge.
Inventors:
Daniel Jay Ramay
Application Number:
JP2000122818A
Publication Date:
February 24, 2010
Filing Date:
April 24, 2000
Export Citation:
Assignee:
Freescale Semiconductor, Inc.
International Classes:
H01L27/04; H01L27/06; H01L21/822; H01L21/8234; H01L27/02; H01L27/088; H01L29/78; H03K17/08
Domestic Patent References:
| JP8222643A | ||||
| JP9181195A | ||||
| JP8331749A | ||||
| JP2070231A | ||||
| JP9298835A | ||||
| JP58014562A | ||||
| JP62287659A | ||||
| JP53110382A |
Attorney, Agent or Firm:
Mamoru Kuwagaki